Message-ID: <8809@brl-tgr.ARPA>
Date: Fri, 1-Mar-85 10:26:23 EST
Article-I.D.: brl-tgr.8809
Posted: Fri Mar  1 10:26:23 1985
Date-Received: Mon, 4-Mar-85 06:02:02 EST
Sender: news@brl-tgr.ARPA
Lines: 19

I tried to install dynamic memory in my CompuPro system (8085/8088). The
board could be strapped for up to 8 wait states so I didn't think that
I would have any problems. I figured that in the worst case 8 wait states
would be alright since the memory was so cheap. Wrong! I put the memory
at 0000H and I couldn't get the 8085 to boot under CP/M since the disk 
controller (DISK1) was too fast for the memory even with 8 wait states. 
I put the memory above my RAM16's and tried to use the 8088 (CP/M86) 
debugger to deposit values in the memory without any luck. The only way
I could get the memory to work was to run my 8085 at 2 MHZ with no wait
states. 

The lesson to be learned is that if you have a disk controller that
does DMA don't buy dynamic memory. 

Dennis    [BRAKE@ARI-HQ1]



------

Message-ID: <523@intelca.UUCP>
Date: Thu, 7-Mar-85 12:10:42 EST
Article-I.D.: intelca.523
Posted: Thu Mar  7 12:10:42 1985
Date-Received: Thu, 7-Mar-85 19:20:02 EST
References: <8809@brl-tgr.ARPA>
Organization: Intel, Santa Clara, Ca.
Lines: 35

 >  I tried to install dynamic memory in my CompuPro system (8085/8088). The
 >  board could be strapped for up to 8 wait states so I didn't think that
 >  I would have any problems. I figured that in the worst case 8 wait states
 >  would be alright since the memory was so cheap. Wrong! I put the memory
 >  at 0000H and I couldn't get the 8085 to boot under CP/M since the disk 
 >  controller (DISK1) was too fast for the memory even with 8 wait states. 
 >  I put the memory above my RAM16's and tried to use the 8088 (CP/M86) 
 >  debugger to deposit values in the memory without any luck. The only way
 >  I could get the memory to work was to run my 8085 at 2 MHZ with no wait
 >  states. 
 >  
 >  The lesson to be learned is that if you have a disk controller that
 >  does DMA don't buy dynamic memory. 
 >  
 >  Dennis    [BRAKE@ARI-HQ1]

Which board was strapped to 8 wait states? If it was your memory the next
question becomes does the disk-1 even recognize waitstates on the bus?
An acquaintence at one of the local computer clubs spent a long time
developing a set of PALs (Programmable Array Logic) that could fully implement
the IEEE TMA (DMA to the rest of the world) spec that did take into account
external ready from the destination or source memory addresses. If done in
individual chips the circuit would have been quite large (he estimates 15 to
20 packages)

I have heard that the problems with Dynamic Ram and DMA were one of the most 
hotly debated subjects at the IEEE-696 meetings. And the end result was a 
workable solution but not many DRAM boards at the time met them. 

--Chuck
-- 
                                            - - - D I S C L A I M E R - - - 
{ihnp4,fortune}!dual\                     All opinions expressed herein are my
        {qantel,idi}-> !intelca!cem       own and not those of my employer, my
 {ucbvax,hao}!hplabs/                     friends, or my avocado plant. :-}

Message-ID: <440@cadovax.UUCP>
Date: Fri, 8-Mar-85 16:17:55 EST
Article-I.D.: cadovax.440
Posted: Fri Mar  8 16:17:55 1985
Date-Received: Sun, 10-Mar-85 07:48:01 EST
References: <8809@brl-tgr.ARPA>, <523@intelca.UUCP>
Organization: Contel Cado, Torrance, CA
Lines: 32

[............]
 >  I tried to install dynamic memory in my CompuPro system (8085/8088). The
 >  board could be strapped for up to 8 wait states so I didn't think that
 >  I would have any problems. I figured that in the worst case 8 wait states
 >  would be alright since the memory was so cheap. Wrong! I put the memory
 >  at 0000H and I couldn't get the 8085 to boot under CP/M since the disk 
 >  controller (DISK1) was too fast for the memory even with 8 wait states. 
 >  I put the memory above my RAM16's and tried to use the 8088 (CP/M86) 
 >  debugger to deposit values in the memory without any luck. The only way
 >  I could get the memory to work was to run my 8085 at 2 MHZ with no wait
 >  states. 
 >  
 >  The lesson to be learned is that if you have a disk controller that
 >  does DMA don't buy dynamic memory. 
 >  
 >  Dennis    [BRAKE@ARI-HQ1]

I have a CompuPro Disk1 that I've been using with an ExpandoRam dynamic
card for years!  The only problem I've ever had with the dynamic RAM card
was in conjunction with an el-cheapo Z-80 CPU card which I believe was
solvable, but I decided to scratch the CPU card anyway.  How fast is the
RAM supposed to be?  is it only 2 MHZ?  I would think that the DMA
speed would be somewhat governed by the rate it's coming off the disk
which ain't that fast.  Are you sure that speed is the problem?  If
by some chance the DMA is being clocked with the CPU's clock, maybe
something can be done to use a divided by 2 clock for the DMA.  However
before attempting something like this, I'd make sure that you really have
your finger on the problem.

Keith Doyle
#  {ucbvax,ihnp4,decvax}!trwrb!cadovax!keithd
"You'll PAY to know what you REALLY think!"

Message-ID: <809@ucbtopaz.CC.Berkeley.ARPA>
Date: Sat, 9-Mar-85 01:08:32 EST
Article-I.D.: ucbtopaz.809
Posted: Sat Mar  9 01:08:32 1985
Date-Received: Tue, 12-Mar-85 10:28:42 EST
References: <8809@brl-tgr.ARPA> <523@intelca.UUCP>
Reply-To: mwm@ucbtopaz.UUCP (Praiser of Bob)
Organization: Missionaria Phonibalonica
Lines: 7
Summary: 

 >  The lesson to be learned is that if you have a disk controller that
 >  does DMA don't buy dynamic memory. 

Please don't tell my Intersystems Box! I'd hate for the DMA to quit working
after 5 years [4 MHz z80, no wait states].

	  

		
		
		
Report message to a moderator

Article-I.D.: watcgl.1452
Posted: Tue Mar 12 10:26:29 1985
Date-Received: Wed, 13-Mar-85 00:08:12 EST
References: <8809@brl-tgr.ARPA> <523@intelca.UUCP> <809@ucbtopaz.CC.Berkeley.ARPA>
Organization: U of Waterloo, Ontario
Lines: 96

 >>  The lesson to be learned is that if you have a disk controller that
 >>  does DMA don't buy dynamic memory. 
 >  
 >  Please don't tell my Intersystems Box! I'd hate for the DMA to quit working
 >  after 5 years [4 MHz z80, no wait states].
 >  
 >  	
no johnny he's too fast! out of my way reed....
FLAME ON!
 The above response is not very useful - "it worked for me...
 must be a law of nature or something I guess :-) "

 The problem is much more complicated than that, simplistic replies
 contribute little.
FLAME OFF!


  I think the point really is that on S100 systems you won't
 know if dynamic memory will  work with your system until you try it;
 then if you change some component sometime down the road everything
  may not be so peachy keen.  As an example some z80 cards bring out
 the z80 refresh signal to the bus which the memory then uses to do
 refresh cycles without causing wait states; if your memory depends
 on this then you will not be able to change cpu's (ever). Another
 aspect is that the term "IEEE/696 compatible" sems to be a *very*
 flexible term in some manufacturers minds so maybe you get a system
 where the cpu or a dma interface isn't quite within specs. A system
 with static memory will probably run with no problems but the weird
 contortions that dynamic memory boards must go through in order to
 maintain refresh while minimizing/eliminating wait states will very
 probably cause it to fail.
 
 Another example : some systems try for an overall io speedup by
 buffering whole disk tracks. An st506 disk will require >3.2 ms
 to transfer just two 1k sectors; the refresh period of the rams
 is 2ms, so unless your disk controller is willing to allow the
 memory to have wait states (which it may very well do - however it
 is *not* to be taken for granted) or the memory can sneak refresh
 cycles in while the interface isn't looking (some try to sync up
 with bus activity and do their refresh cycles after a memory
 access, which because of the speed of an st506, would work in this
 case) then your system will not work.
 
 Another example : because of the way static rams are set up you
 can leave the chips enabled all the time and feed in the address
 bus continually to the chips; when the control circuitry on the
 board decides the board is actually being addressed for a memory
 cycle it can gate the data lines to/from the chips and set the
 read/write enable appropriately.  Beacuse of the timing of most
 of the micros there is a significant delay between the address
 appearing on the bus and the control/status information describing
 the cycle appearing on the bus - using the above technique (which
 is implemented on a board I own) can decrease board access time
 by significant amounts (50-100 ns).  The way that addresses are
 gated into drams (and cycles initiated) precludes doing this.
 
 and on and on and on and on.......
 
 Opinion: do not buy a dram board unless you know (or someone you
          trust tells you) that it will work in the configuration
          in which you plan to use it; if you buy it be prepared
          to have to throw it out if you ever want to change any
          part of your system that does dma (including/especially
          the cpu).
 
 Opinion: if you buy everything from the same manufacturer it will
          probably all work but eventually you will have the same
          problem as above (unless the same manufacturer also makes
          the new board as well).

 Opinion: I think that one of the big reasons for the decline of
          S100 popularity is dynamic memory - for what it costs
          to buy one 64k static board for an s100 you can get
          256k dynamic boards (that work) for pc clones; I mean
          geez, for the price of one Compupro 256k static board
          you can get a complete sanyo mbc, with disk drive,
          monitor, software, and 256k.  I think this is a crying
          shame - s100 systems are flexible and do not commit
          you to a single manufacturer, the bus interface is
          actually very simple and the entire s100 concept
          encourages proliferation of ideas, products and concepts.
          Micros today seem to be heading towards a very mainframe
          mentality - medicority dominates.
 
 Opinion: There is no reason why a good s100 dynamic board could
          not be made for <500 with 1mbyte of no wait state (and
          refesh states <5% of the time) memory, given the LSI
          dram controllers available and the current price of
          256k chips. Just keep to the standard.
   and on and on and on ......
 
 Sorry to be so lengthy,
 
        John Chapman
 
 ...!watmath!watcgl!jchapman

Article-I.D.: acf4.1010008
Posted: Fri Mar 15 21:24:00 1985
Date-Received: Sun, 17-Mar-85 22:05:24 EST
References: <8809@brl-tgr.ARPA>
Organization: New York University
Lines: 42

<<<>>>

From my (minimal) knowledge about chip design, I seem to recall that for
a given technology (say NMOS), a single bit of a static ram consisted of
a master slave flip flop which retains its value once set. On the other hand
a bit from a dynamic ram could be made quite simply from two transistors and
two inverters in the form:

                |
               ___
               ___
              |   |          |    = transistor
           ___|   |______   ---  
           |            |
      |    |            o    >o   = inverter
     ___   |            ^
     ----------->o------|

and that the above could be refreshed by a 2 phase clock since the charge
eventually leaks. From this I can conclude that dynamic rams can be made
denser and faster than static rams (master slave flip flops require much
more logic per bit). Since the charge does not leak that often (say once
a minute or so in room temperature) and that they use so much less logic,
they should also consume less power than static rams. Also the above dynamic
ram design is suitable for implementation in VLSI.

Why then is a 256K static ram board $1500 and 256K of dynamic ram chips
merely $100? Why can I get static ram which will run with a 12 Mhz 68000,
a 8 Mhz 80286 and a 8Mhz Z80 and not dynamic ram which will do the same?
Why does every one advertise static ram as "low power". Am I looking at
different technologies (NMOS vs CMOS)? What is the S-100 standard for 
providing a signal to the ram board for dynamic ram refresh? If there is
why doesn't everyone adhere to it? I also believe that a dynamic ram 
controller such as the Intel 8203 has an internal timer which will provide
fail safe refresh. Other than that to minimize wait states due to refresh
cycles, one could generate a refresh request whenever a bus cycle occurs
and memory is not accessed (for example during an I/O cycle)


                                           Sam Chin
                                           allegra!cmcl2!acf4!tsc2597
                                           tsc2597.acf4@nyu

Article-I.D.: watcgl.1488
Posted: Mon Mar 18 09:46:21 1985
Date-Received: Tue, 19-Mar-85 03:37:50 EST
References: <8809@brl-tgr.ARPA> <1010008@acf4.UUCP>
Organization: U of Waterloo, Ontario
Lines: 63

 >  Why then is a 256K static ram board $1500 and 256K of dynamic ram chips
 >  merely $100? Why can I get static ram which will run with a 12 Mhz 68000,
 >  a 8 Mhz 80286 and a 8Mhz Z80 and not dynamic ram which will do the same?
 >  Why does every one advertise static ram as "low power". Am I looking at
 >  different technologies (NMOS vs CMOS)? What is the S-100 standard for 
 >  providing a signal to the ram board for dynamic ram refresh? If there is
 >  why doesn't everyone adhere to it? I also believe that a dynamic ram 
 >  controller such as the Intel 8203 has an internal timer which will provide
 >  fail safe refresh. Other than that to minimize wait states due to refresh
 >  cycles, one could generate a refresh request whenever a bus cycle occurs
 >  and memory is not accessed (for example during an I/O cycle)
 >  
 >  
 >                                             Sam Chin
 >                                             allegra!cmcl2!acf4!tsc2597
 >                                             tsc2597.acf4@nyu
 
 1. current prices are more like $1000 for 256k static boards and
    $600 for 256k dynamic (not quite as big a price difference as
    you have indicated.
 
 2. drams are generally denser (x4) than statics.
 
 3. dynamic ram chips are themselves much cheaper than static, probably
    due in part to the fact that mainframe manufacturers use zillions
    of them and therefore spread (chip) costs over a larger base.
 
 4. there is no s100 standard for a refresh signal, this is precisely
    the problem
 
 5. why does static always work? because all it does is read/write
    cycles -> simpler board design, timing requirements etc.  On the
    other hand dynamic has to make sure it gets (64/128/256) refresh
    cycles every 1 or 2 ms.  The bus standard makes no allowance for
    this so the memory board has to squeeze them in whenever it
    thinks it is safe.  The failsafe refresh you refer to is from
    the ram chips point of view - the 8203 will always keep it
    refreshed - not from the bus masters point of view ( to take
    things to an absurd point: you could have the ram controller
    devote 100% of cycles to refresh, which would be failsafe but
    is not something you are likely to be happy with).
 
 6. Using i/o cycles to do hidden refresh will not help much (how
    much of the bus time is spent doing this).  The big problem
    is that you have to come up with a scheme that guarantees
    adequate refreshing 100% of the time (99.99999% is not good
    enough).  The bus standard is precisely that - it places
    certain requirements on the signals on the bus and not really
    on the cpu - e.g. all refreshing eventually depends on being
    able to stall the current bus master to do a refresh cycle;
    an 8086 wants the ready signal/status during T2, if you design
    a board to accomodate this will it also fulfill the requirements
    of a dma disk controller? or a Z80? or a 68000? or a Z8000?
    or a 32016? or a 6800? (Gods reputed action at the tower of babel
    was viewed as a curse for good reason :-).

 7. If you could guarantee strict adherence to the timing in
    IEEE/696 of all the cpu boards and dma boards that you want
    to use then it should certainly be possible to contruct a
    dynamic board for the s100 that would work in all situations
    but it by no means a trivial task.
 
    John