Message-ID: <1135@sun.uucp>
Date: Tue, 22-May-84 11:48:38 EDT
Article-I.D.: sun.1135
Posted: Tue May 22 11:48:38 1984
Date-Received: Wed, 23-May-84 19:32:10 EDT
References: <2539@ecsvax.UUCP>
Organization: Sun Microsystems, Inc.
Lines: 20

Yes, it's very useful.  In particular, a FAST flip-flop is the
best synchronizer I know of.  F74's and F374's settle out of
a metastable condition (caused by missing a setup or hold time)
in about 35 nsec, whereas S74's take about twice as long.  LS is
just about hopeless in this case.

FAST is also very useful when you need short prop delays.  It uses 
significantly less power than Schottky, with similar delays.

One area where FAST is not so good is in driving busses.  The fall
time is so short that it is difficult to control crosstalk on a bus
driven by FAST logic.  I talked to the product planning guy from Fairchild
yesterday and mentioned this problem.  He says that other customers
have mentioned this also, so thay are going to think about doing
a class of FAST parts with reduced edge rates.

Mitch Bradley
Sun Microsystems, Inc.
sun!wmb
 

Message-ID: <4674@amd70.UUCP>
Date: Wed, 23-May-84 15:52:14 EDT
Article-I.D.: amd70.4674
Posted: Wed May 23 15:52:14 1984
Date-Received: Fri, 25-May-84 01:00:21 EDT
References: <1135@sun.uucp>
Organization: AMD, Santa Clara, CA
Lines: 4

Does anyone know how AS compares with FAST for metastable settling time?

-- 
Phil Ngai (408) 749-5286 {ucbvax,decwrl,ihnp4,allegra,intelca}!amd70!phil

Message-ID: <591@decwrl.UUCP>
Date: Fri, 25-May-84 08:41:22 EDT
Article-I.D.: decwrl.591
Posted: Fri May 25 08:41:22 1984
Date-Received: Sat, 26-May-84 02:23:15 EDT
Organization: DEC Engineering Network
Lines: 10

I don't know about AS settling times, as I haven't used any AS chips, but I
believe that the fastest metastable settling times are those of the AMD
2982x series of registers.  They appear to be good at under 30 ns.  But I'd
say that FAST is useful over AS primarily because of its significantly lesser
power consumption.

Cheers,
Dick Binder
UUCP:  {decvax|allegra|ucbvax|}!decwrl!rhea!dosadi!binder
ARPA:  binder%dosadi.DEC@decwrl.ARPA

Message-ID: <400@turtlevax.UUCP>
Date: Fri, 25-May-84 21:50:46 EDT
Article-I.D.: turtleva.400
Posted: Fri May 25 21:50:46 1984
Date-Received: Mon, 28-May-84 06:11:45 EDT
References: <591@decwrl.UUCP>
Organization: CADLINC, Palo Alto, CA
Lines: 9

I don't know about the rest of you guys, but I'm convinced that the
only chips usable for clock drivers are the 74AS804 NAND gates and
74AS1004 inverters.  Most of the other AS stuff doesn't seem to be as
impressive.  TI seems to be putting more of its eggs in the ALS basket,
taking advantage of the better speed/power tradeoff to give people what
they are already using.
-- 
Ken Turkowski @ CADLINC, Palo Alto, CA
UUCP: {amd70,decwrl,flairvax}!turtlevax!ken

Message-ID: <488@cygnet.UUCP>
Date: Sat, 26-May-84 15:43:38 EDT
Article-I.D.: cygnet.488
Posted: Sat May 26 15:43:38 1984
Date-Received: Wed, 30-May-84 00:10:23 EDT
References: <591@decwrl.UUCP>
Organization: Cygnet Systems -- Sunnyvale, CA
Lines: 17

[I hope this works - this is my first posting]
I'm curious about where you guys are getting your numbers for 
metastable settling times.  About 6 years ago I did some playing 
around in the lab trying to induce metastability in LS, ECL 10k, and 
CMOS, but my attempts were rather clumsy and could only give me a 
general feel for the characteristics of the family.  

I had the idea of doing an analysis of the behavior of various logic 
families using SPICE, but figured that to do it properly would require 
getting device characteristics from the chip houses.  I assumed that 
they would not be willing to let the information out.  

Do any of you know of serious work that characterizes the various
families and is in the public domain?

Bob Clark
Cygnet Systems, 610 Palomar Ave., Sunnyvale, CA 94086 (408)773-0770

Message-ID: <3925@utzoo.UUCP>
Date: Sat, 2-Jun-84 18:47:25 EDT
Article-I.D.: utzoo.3925
Posted: Sat Jun  2 18:47:25 1984
Date-Received: Sat, 2-Jun-84 18:47:25 EDT
References: <2539@ecsvax.UUCP>, <1135@sun.uucp>
Organization: U of Toronto Zoology
Lines: 18

Thinking of edge rates brings to mind something I've been curious about
for some time.  The spec sheets for practically any digital logic give
a maximum edge time, for obvious reasons.  But one or two spec sheets --
notably for the 64K DRAMs -- also specify a *minimum* edge time.  Does
anybody know why?  (I'm not up on the intricacies of MOS VLSI.)  Is
this just a matter of "our testers won't run any faster than this, and
we won't guarantee behavior we don't test", or is there some problem
with very fast edges?

Specifically, suppose that I'm driving 64Ks with 74F drivers, and I'm
half-asleep and hence have forgotten the series damping resistors.  The
poor DRAM is now getting a direct look at those sizzling-fast 74F edges.
Will it go up in a puff of glittering smoke?  Will it just refuse to work?
Will it hold a secret grudge against me, so that it fails later when I'm
depending on it?  Or what?
-- 
				Henry Spencer @ U of Toronto Zoology
				{allegra,ihnp4,linus,decvax}!utzoo!henry

Message-ID: <569@dual.UUCP>
Date: Wed, 6-Jun-84 11:38:14 EDT
Article-I.D.: dual.569
Posted: Wed Jun  6 11:38:14 1984
Date-Received: Thu, 7-Jun-84 19:40:06 EDT
References: <591@decwrl.UUCP> <400@turtlevax.UUCP>
Organization: Dual Systems, Berkeley, CA
Lines: 8

Why are we getting so many duplicate articles? Okay, this probably
doesn't belong in this newsgroup, but there seem to have been an
awful lot of duplicate articles *WITH NEW DATES* coming through the
net recently, and I would much like to know why....

	    Mats Wichmann
	    Dual Systems Corp.
	    ...{ucbvax,amd70,ihnp4,cbosgd,decwrl,fortune}!dual!mats