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From: tim@cayman.amd.com (Tim Olson)
Newsgroups: comp.lang.forth
Subject: Re: Cost of Forth Chips
Message-ID: <26815@amdcad.AMD.COM>
Date: 17 Aug 89 15:17:44 GMT
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In article <5882@pt.cs.cmu.edu> koopman@a.gp.cs.cmu.edu (Philip Koopman) writes:
| Pipelining does not affect the consistency of response in
| a real time program, but it does affect the interrupt response
| latency, since you have all that state to save when processing
| an interrupt.

What pipeline state do you need to save when responding to an interrupt? 
Everything in the pipeline before the "commit point" is flushed, while
everything after the commit point continues on through the pipeline. 
This all happens pretty much instantaneously.

	-- Tim Olson
	Advanced Micro Devices
	(tim@amd.com)