Path: utzoo!mnetor!uunet!husc6!uwvax!oddjob!gargoyle!att-ih!pacbell!ames!oliveb!pyramid!decwrl!hplabs!ucbvax!GULL.ULOWELL.EDU!lechner
From: lechner@GULL.ULOWELL.EDU (Bob Lechner)
Newsgroups: comp.lsi
Subject: Re:  Available Hardware Testers (inexpensive)
Message-ID: <8804070200.AA04146@gull.ulowell=edu>
Date: 7 Apr 88 02:00:16 GMT
Sender: daemon@ucbvax.BERKELEY.EDU
Organization: The Internet
Lines: 11

I just read your msg. on vlsi network last year. How have yo made out 
on VLSI tester acq. or design? The organization m2c.m2c.org is buying
testers of some type for MA. eng . schools. It may have info.
Contact: pcohen or lipton@m2c.org

I have ben trying to design a functional tester withg a PC host,
in a comp eng course preceding a VLSI course.
30-50MHz clock rate, samppling scope approach to output data acquisition.
Any ideas on this?
RAM input at slower clock cycles, pattern generation within each cycle,
video RAMS as data sources and sinks