Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!utgpu!water!watmath!clyde!rutgers!gatech!mcnc!rti!dg_rtp!meissner From: meissner@dg_rtp.UUCP Newsgroups: comp.arch Subject: Re: Japanese 32-bit CPUs ( NEC V70 ) [really CISC] Message-ID: <1920@dg_rtp.UUCP> Date: Sat, 16-May-87 17:37:23 EDT Article-I.D.: dg_rtp.1920 Posted: Sat May 16 17:37:23 1987 Date-Received: Sun, 17-May-87 02:52:58 EDT References: <609@csun.UUCP> Reply-To: meissner@dg_rtp.UUCP (Michael Meissner) Organization: Data General (Languages @ Research Triangle Park, NC.) Lines: 58 > In article <277@astroatc.UUCP> johnw@astroatc.UUCP (John F. Wardale) writes: > > >Now the trend is to build simpler, faster REGULAR machines, and the only > >thing that falls the the category of "fashionability" is terms "RISC" and > >"CISC" Seymore (sp?) made a RISCy machine called the "Cray-1" before > >anyone started to use the term "RISC" ... And in article <609@csun.UUCP> aeusesef@csun.UUCP (Sean Eric Fagan) replies: > > Not to be nitpicky, or anything, but old Seymore did a RISC long before the > Cray-1. Ever hear of the CDC Cyber line? The 6600, 7600, 170 lines? All > RISC, with a grand total of about, oh, 70+ instructions. Two instructions > to directly access memory, and a few instructions to indirectly access > memory. .... > Very fast floating point, slightly slower integer (yeah, > slower), very nice instruction set. While the 6600 and 7600 lines had a sparse number of instructions, I doubt whether they would qualify as a RISC machine (I don't know about the CRAY). In the first place, the main thing about ALL of the RISC's that are true RISC's, is that EVERY instruction takes one cycle. No exceptions. The CDC machine instructions could take multiple cycles (divide in particular). One of the things that highlighted the machines was multiple parallel functional units (ie, you would typically fire off a divide, and then multiplies, each with different accumulators, and as long as you did not issue an instruction using that accumulator until the unit was done, you could proceede and do something else). Another thing that the RISC philosophy has come to mean is regular (ie, no special purpose accumulator's, any register can be the target or source(s) of any instruction). I dare you to call this machine regular. To load from main memory, you stored the address you wanted into an A register (A1-A5 only), and in a few cycles the value would appear in the corresponding X register. To store a value, you would store the address into an A register (A6-A7 only), and the corresponding X register would be stored. Thus the X registers were special purpose (X1-X5 could read from memory, X6-X7 could write to memory, X0 was scratch). The A registers were tied to the corresponding X registers, and only 18 bits wide. The B registers were also 18 bits wide, with B0 being hardwired to 0 (you could store into B0, but the machine would ignore it). Given the parallel functional units, the machine kept track of which accumulator was in use, and would pend any instruction that would reference it, until the functional unit was done (unlike some recent machines, where the compiler would have to do the scheduling itself because the hardware interlock was removed for speed). The Fortran compiler (FTN) would attempt to keep the different functional units busy. Also, given that the machine wordsize (60 bits) was much larger than the instruction size (mostly 15 or 30 bits), any instruction that was the target of a branch had to begin on a word boundary. Because of parallel functional units and up to 4 instructions per word, faults were only approximate (you knew which word faulted, but not which instruction in the word). It also became a game of assembler hackers to conconct things like a sequence that would raise three different faults (overflow, underflow, etc) in the same machine word. It was an interesting machine. -- Michael Meissner, Data General Uucp: ...mcnc!rti!dg_rtp!meissner It is 11pm, do you know what your sendmail and uucico are doing?