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From: preece@ccvaxa.UUCP
Newsgroups: comp.arch
Subject: Re: Japanese 32-bit CPUs ( NEC V70
Message-ID: <28200037@ccvaxa>
Date: Mon, 11-May-87 11:29:00 EDT
Article-I.D.: ccvaxa.28200037
Posted: Mon May 11 11:29:00 1987
Date-Received: Thu, 14-May-87 05:53:04 EDT
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Nf-From: ccvaxa.UUCP!preece    May 11 10:29:00 1987


  mash@mips.UUCP:
> If somebody says "20 addressing modes are good", to be convincing,
> they'd better be able to show tradeoffs, and show us the dynamic and
> static usages of those things, in real compiled code of substantial
> size.  They may be worth it, or they may be not, but there is
> substantial data that says that complex addressing modes just aren't
> used very much.  Perhaps this is an exception....
----------
I find it a little amusing that the same people who say "complex
feature x just isn't used very much" tend to be the same people who
say "not to worry, a sufficiently clever compiler will take care of
our ship's need for X".  If compilers can be made smart enough to
handle some of the special things that RISCs need, they could be
made smart enough to make better use of the complex features in
CISCs.

The point isn't that RISCs make certain optimizations easier or harder,
but that they make certain optimizations NECESSARY.  Compilers smart
enough to use some of the special features of CISCs haven't been
sufficiently necessary -- they work "well enough" using simple
instruction sequences.  My impression from the literature is that RISCs
demand more compiler optimization to reach the performance that is
expected of them than do CISCs.  Perhaps that simply means we have
higher expectations of them, perhaps it simply means that baseline
compiler performance is better than it used to be and those expectations
are reasonable.  Whatever.

-- 
scott preece
gould/csd - urbana
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