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From: lm@cottage.WISC.EDU (Larry McVoy)
Newsgroups: comp.arch,comp.sys.nsc.32k
Subject: Re: Performance of the 532
Message-ID: <3552@spool.WISC.EDU>
Date: Fri, 8-May-87 01:31:02 EDT
Article-I.D.: spool.3552
Posted: Fri May  8 01:31:02 1987
Date-Received: Sat, 9-May-87 16:39:41 EDT
References: <324@dumbo.UUCP> <809@killer.UUCP> <2417@homxa.UUCP> <4294@nsc.nsc.com> <374@winchester.UUCP>
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Reply-To: lm@cottage.WISC.EDU (Larry McVoy)
Organization: U of Wisconsin CS Dept
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Xref: mnetor comp.arch:1214 comp.sys.nsc.32k:137

In article <374@winchester.UUCP> mash@winchester.UUCP (John Mashey) writes:
>Could you say a little more on the configurations:
>	cache size, nature [write-back or write-thru]
>	if write-thru, did you use write buffers, and if so, how deep.
>	exactly what the assumptions were on the VME memories

If they are following their data book, then

    Icache is 512 bytes, 32 lines, direct mapped.
    Dcache is 1024 bytes, 64 lines, 2 way set associative, write through.
    TLB is 64 entries, fully associative.

>It would also be interesting [although I realize this might be
>sensitive info] to get more info on the simulations, to be able to
>make a read on the accuracy of the simulations:
>
>	instruction cycles
>	TLB-miss cycles
>	cache-miss cycles
>	[if present] write-buffer stall & write/read interlock cycles

I'd like to see this too.

Also, I'm a little surprised at the figures.  I just spent a bit of time
going over the data book and I would have expected better numbers.  
Closer to 8-10 MIPS...  Bummer....

---
Larry McVoy 	        lm@cottage.wisc.edu  or  uwvax!mcvoy

"What a wonderful world it is that has girls in it!"  -L.L.