Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!seismo!husc6!rutgers!lll-lcc!pyramid!prls!mips!mash From: mash@mips.UUCP (John Mashey) Newsgroups: comp.arch Subject: Re: Japanese 32-bit CPUs ( NEC V70 ) [really 29K] Message-ID: <372@winchester.UUCP> Date: Wed, 6-May-87 21:59:24 EDT Article-I.D.: winchest.372 Posted: Wed May 6 21:59:24 1987 Date-Received: Sat, 9-May-87 01:57:52 EDT References: <3810030@nucsrl.UUCP> <491@necis.UUCP> <3530@spool.WISC.EDU> <4016@necntc.NEC.COM> <16561@amdcad.AMD.COM> Reply-To: mash@winchester.UUCP (John Mashey) Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 38 Keywords: V60, V70 In article <16561@amdcad.AMD.COM> bcase@amdcad.UUCP (Brian Case) writes: >In article <4016@necntc.NEC.COM> pec@necntc.UUCP (Paul Cohen) writes: >>It depends on its objectives. The 29K requires two separate >>paths to memory, one for code and another for data. The memory must be >>extremely fast (read expensive) to service the CPU without wait states. 2 paths are usually better than one, as any chips will discover when they keep pushing clock rates. >case). Let's face it: you can try lots of stuff with instruction set >encoding, pipelinging tricks, etc. etc., but in the end, the performance >of the CPU comes down to that of the memory hierarchy. agree. I did have one question: what kind of write buffers do the AMD simulations use [i.e., how deep], and what kind of % hit is there for: a) write stalls [write buffer full] b) read/write memory conflicts [i.e., I was already doing a write, and a read comes along that's a cache miss]. If I missed this info published somewhere, just point us at it. > >optimizations *easier* not more difficult. I believe that most of >the members of the compiler-writing and architecture community would >agree that a simple architecture with a predictable cost for instructions >(in both time and space) is the best match for automatic code generation. 100% we may disagree on other issues, but not this one. [following on the earlier comments on V70 addressing modes] If somebody says "20 addressing modes are good", to be convincing, they'd better be able to show tradeoffs, and show us the dynamic and static usages of those things, in real compiled code of substantial size. They may be worth it, or they may be not, but there is substantial data that says that complex addressing modes just aren't used very much. Perhaps this is an exception.... -- -john mashey DISCLAIMER:UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mash, DDD: 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086