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From: geoff@callan.UUCP (Geoff Kuenning)
Newsgroups: net.micro.68k
Subject: Re: The 68010 and MMU's
Message-ID: <210@callan.UUCP>
Date: Fri, 27-Jul-84 09:38:09 EDT
Article-I.D.: callan.210
Posted: Fri Jul 27 09:38:09 1984
Date-Received: Mon, 30-Jul-84 00:22:08 EDT
References: <2083@rlgvax.UUCP>
Organization: Callan Data Systems, Westlake Village, CA
Lines: 45

Jack Slingwine gave an excellent summary of the major 68010 differences in his
note.  However, I cannot resist sticking my nose in and pointing out a few
more things:

The 68010 has generally speeded-up instructions compared to the 68000;  we
find about a 15% improvement when running at the same clock speed.  The
speedups are mostly in the common instructions:  moves, adds, etc.  This
is probably the biggest payoff of having a 68010 in a non-MMU system.

The 68010 has more lenient bus-error timing.  This can be a factor in an ECC
memory design which reports ECC problems with bus errors, since ECC status is
typically available quite late in a memory cycle.

I was looking up some 68010 instruction execution times and discovered
something interesting:  the "loop mode" is still not the fastest way to
move memory.  The execution time for "movl a0@+,a1@+" in loop mode is
22 clocks (loop continued;  I am assuming a large block of memory).  On
the other hand, if you use move multiple (as discussed previously in this
newsgroup) you must execute four instructions:  "moveml a0@+,#mask" where
'mask' specifies 12 registers, "moveml #mask,a1@", "addl #12*4,a1", and
"dbra d0,loop".  This all takes  236 clocks per pass, compared with 264 clocks
for an equivalent amount of moving in loop mode.  On the other hand, you
have to do a divide instruction (122 cycles) to get the loop counter; this
only pays off if you have more than 60 longwords to move.

MMU's:

The 68451 is a great MMU if you have a segmented architecture with very few
(32 or less) segments.  Since the PDP-11 had only 8, Unix fits quite well on
such an MMU.  Unfortunately, the 451 introduces at least one wait state, so
you have to pay CPU performance unless you introduce a cache ahead of the MMU.
When you get to going virtual on a 68010, however, the 451 simply can't hack
it.  Not enough distinctly identifiable pages.

The 68881 Paged MMU has been formally announced, but no silicon has actually
seen the light of day.  I have seen some specs;  it is a pretty neat and
flexible little device--one of those satisfy-everybody (once you figure out
how to set it up) jobbies in the USART/PIO mold.  There is some doubt among
my rumormongers that the chip will ever actually come to fruition--but then
I heard that about the 020.
-- 

	Geoff Kuenning
	Callan Data Systems
	...!ihnp4!wlbr!callan!geoff