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From: howard@metheus.UUCP (Howard A. Landman)
Newsgroups: net.jobs
Subject: VLSI Designer & CAD Programmer
Message-ID: <260@metheus.UUCP>
Date: Thu, 9-Aug-84 18:51:57 EDT
Article-I.D.: metheus.260
Posted: Thu Aug  9 18:51:57 1984
Date-Received: Sat, 11-Aug-84 00:48:31 EDT
Organization: Metheus, Portland Oregon
Lines: 241

I am looking for a technical leadership role in the general area of IC design
and CAD software development.  This means that I want to BOTH be involved in
designing ICs or helping others to design ICs, AND building CAD tools to
improve the design process.  Startups are especially welcome.
Please contact me at home at (503) 640-6625 or via U.S. Mail at
725 E. Main, Hillsboro OR  97123, as my net address may shortly vanish.
A two-page resume follows in "vtroff -me" format:
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.ce 2
.sz 12
.b
Howard A. Landman
.br
.i
VLSI Designer and CAD Programmer
.sz 10
.sp 2
.uh Education
.ip
MS Computer Science,
University of California, Berkeley,
6/82
.ip
BA Mathematics (with honors),
University of California, Berkeley,
8/73
.uh Experience
.lp
.(b L
.r
6/82 to present:
.i
VLSI/CAD Designer
.r
Metheus Corporation, Hillsboro, OR
.)b
.ip
Principal software engineer for 10 programs
included in Metheus' CAE workstation;
also contributed to several other programs.
All work in C under UNIX on VAX or 68000.
Supervised one programmer.
Negotiated with foundries such as AMI and IMP,
leading to technology exchange agreements.
Several months of technical marketing work including much travel.
.lp
.(b L
6/81 to 6/82:
.i
Director of Software Engineering
.r
SynMos Corporation, Palo Alto, CA
.)b
.ip
Developed and maintained CAD environment for IC design,
including configuration of mainframe and workstations
and integration of software packages.
Managed software developers.
Helped teach introductory VLSI design courses.
Provided design assistance service to customers.
Designed test patterns and circuits
to evaluate fabrication quality,
and screened incoming wafers.
Designed standard library cells for use in classes.
.lp
.(b L
1979 to 1981:
.i
Research Intern
.r
Xerox Corporation, Palo Alto Research Center, Palo Alto, CA
.)b
.ip
Enhanced and maintained interactive text/graphics system
for managing process and run data for NMOS fabrication facility.
Designed circuits and test patterns for process characterization.
.lp
.(b L
1978 to 1979:
.i
Systems Engineer
.r
Fujitsu Limited, Sunnyvale, CA
.)b
.ip
Surveyed various aspects of U.S. computer industry.
Gathered information from literature and other sources.
Attended conferences and lectures.
Analyzed data and prepared reports for home offices in Japan.
.lp
.(b L
1976 to 1978:
.i
Business Planner, Financial Systems Analyst
.r
Amdahl Corporation, Sunnyvale, CA
.)b
.ip
Studied computer software vendors and market
in relation to corporate strategy.
Identified and evaluated acquisition candidates, products, technical expertise.
Prepared 200 page report of findings.
Presented recommendations to corporate officers.
Supervised two employees.
Interfaced with programmers and vendors
for selection, design, implementation and evaluation of accounting programs.
.lp
.(b L
.i
Process Computer Analyst
.r
General Electric Co., Nuclear Energy Division, San Jose, CA
.)b
.ip
Helped develop a fast approximation scheme for neutron flux in reactor cores,
and test it against detailed simulations.
Techniques included pattern recognition, linear regression,
and symmetry group theory.
.lp
.(b L
.i
Teaching Assistant
.r
University of California, Computer Science Division, Berkeley CA
.)b
.ip
Twice assisted in teaching VLSI design course.
Counseled students on use of CAD tools,
good design practices,
and other issues related to design of NMOS ICs.
Coordinated submission of completed chips for fabrication.
.uh Publications:
.ip
"OPUSI: An Optical Digital Position Sensor",
.i
ICCAD 83 Digest of Technical Papers,
.r
September 1983
.ip
"Integrating Foundry Processes into the Engineering Workstation",
.i
Electro/83 Professional Program,
.r
April 1983
.ip
.i
Automatic Layout of Optimized PLA Structures,
.r
Master's Thesis & ERL Memo,
U.C. Berkeley,
1982
.ip
"PLA Tools", in
.i
Berkeley VLSI Tools,
.r
Bob Mayo (ed.),
Computer Science Division, U.C. Berkeley,
1982
.ip
"A RISCy Approach to VLSI",
.i
VLSI Design,
.r
4th quarter 1981
.ip
"VLSI Implementations of a Reduced Instruction Set Computer",
.i
CMU Conference on VLSI Systems and Computations,
.r
1981
.uh "Chips designed:"
.ip
.i
HORUS boustrophedon:
.r
Unusual analog position sensor
using coupled light-controlled oscillators
and switched capacitor.
44 FETs.
(in fab)
.ip
.i
OPUSI:
.r
A digital position sensor
incorporating 256 photodiodes and 69,000 FETs
on a single chip.
Extremely regular design.
(worked on first fab at both 4um and 3um)
.ip
.i
RISC:
.r
Reduced Instruction Set Computer (with many other designers).
44,000 FETs.
(worked on first good fab)
.ip
.i
XIB:
.r
X-Port Input Buffer (with Ion Ratiu and Joe Decuir).
Multi channel inchworm FIFO for the X-Tree project.
Included on-chip error correction (SEC/DED).
5,000 FETs.
.ip
.i
XHEC:
.r
Hamming Encoder/Decoder/Corrector for XIB (with Ion Ratiu).
.ip
.i
XFIFO:
.r
Single FIFO cell for XIB.
.ip
.i
RPLA:
.r
Reprogrammable Logic Array.
.ip
.i
TALLY:
.r
Implementation of Mead-Conway Tally Circuit.
(worked on first fab)
.ip
.i
SynMosTP:
.r
Wafer acceptance test pattern for SynMos Corp.
.ip
.i
TP1180, TP780, TP580, TP380:
.r
Test patterns for Xerox PARC fab line.
.uh Interests:
.ip
Go, Aikido, Tai Chi, music (guitar, synthesizer), mountaineering,
backgammon, jogging
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