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From: kds@intelca.UUCP (Ken Shoemaker)
Newsgroups: net.micro
Subject: Re: Microprocessor Performance Context
Message-ID: <195@intelca.UUCP>
Date: Fri, 3-Feb-84 15:41:14 EST
Article-I.D.: intelca.195
Posted: Fri Feb  3 15:41:14 1984
Date-Received: Wed, 8-Feb-84 09:07:24 EST
References: <825@hao.UUCP>
Organization: Intel, Santa Clara, Ca.
Lines: 34

I feel compelled to respond to this note, I hope that what I say
makes sense...

	Also  since  multiplexing  affects  [e.g.,  reduces]
	performance  by  about  25 percent,  it  is  proposed  that  when
	describing processors  the  use of a slash  (/)  to indicate that
	the address and data paths are multiplexed and a plus sign (+) to
	show that the address and data paths are separate is appropriate.

This is true only if the address time and data times on the bus overlap.
For something like a 68000 this is not true, address information does
not become available until after a bus cycle has started, well after
the data access of the previous bus cycle has completed.  Since the address
and data times DO NOT overlap, no performance gain is achieved...It still
takes the 68000 at least 4 clock cycles to access anything, exactly
as it takes the 8086 at least 4 clock cycles, even though the 68000 has
a non-multiplexed bus and the 8086 has a multiplexed bus.  The 286
(non-multiplexed address and data), on the other hand
starts another memory access BEFORE the end of the previous
bus cycle, thus allowing improved performance by overlapping
the memory access times between two bus cycles.  To realize the performance
improvement you need to interleve memories (or you could also play around
with select circuitry) which the 8207 DRAM controller automatically does
for you.

	[Note that I have expanded, altered,  and somewhat shuffled the above
	tabulation, (for one thing, I reduced the 68000 and 68010 from 24 to
	23 address bits pinned out) thus any slurs, unintentional or otherwise,
The 24th address bit would be a byte selection, so there are still 24
address lines selecting bytes (8 bit), 23 address lines selecting words 
(16 bit).
-- 
Ken Shoemaker, Intel, Santa Clara, Ca.
{pur-ee,hplabs,ucbvax!amd70,ogcvax!omsvax}!intelca!kds