Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!linus!decvax!harpo!seismo!hao!hplabs!sri-unix!GUBBINS@RADC-TOPS20.ARPA From: GUBBINS@RADC-TOPS20.ARPA Newsgroups: net.micro Subject: S-100 Sound board design Message-ID: <16699@sri-arpa.UUCP> Date: Fri, 17-Feb-84 09:53:10 EST Article-I.D.: sri-arpa.16699 Posted: Fri Feb 17 09:53:10 1984 Date-Received: Mon, 20-Feb-84 02:04:26 EST Lines: 26 From: GernAs per SMITH prodding, I have examined the concept of uprating my 3 channel 2 I/O port desing to 6 channel, 4 I/O port design. I thought I could pull it off using 3 less chips (no longer need to multiplex I/O) at a cost of $10 more. A patch on my current, stable working 3 channel design indicates that just one buffer now needed on an address line so as to not blow IEEE-696 spec of the new design blows up the PSG chips timming by 10nsec yielding it don't work no more without adding I/O wait circuitry which I have been trying to avoid (note use of run-on sentance to match my run-on thoughts) When I have some time soon I will look at everything again and try to arrive at once again an optimal design and start work on a PC layout and a new prototype , as I don't want to touch my current working 3 channel board. I thought I was cutting my timming kinda fine, but 10 nsec??? Wish me luck. Cheers, Gern -------